LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

entity ContadorBCD is
port(
	rst : in std_logic;
	ck: in std_logic;
	ei: in std_logic;
	q0 : out std_logic;
	q1 : out std_logic;
	q2 : out std_logic;
	q3 : out std_logic;
	eo : out std_logic);
end;

architecture mix of ContadorBCD is
	signal d0,d1,d2,d3: std_logic;
	signal q0_s,q1_s,q2_s,q3_s: std_logic;
	component ffd
		port(
  clr: in std_logic;
  ck: in std_logic;
  d: in std_logic;
  e:in std_logic;
  q: out std_logic;
  nq: out std_logic 
		);
	end component;
begin
	ffd0: ffd port map ( rst,ck,d0,ei,q0_s,open);
	ffd1: ffd port map ( rst,ck,d1,ei,q1_s,open);
	ffd2: ffd port map ( rst,ck,d2,ei,q2_s,open);
	ffd3: ffd port map ( rst,ck,d3,ei,q3_s,open);

 	d0 <= not q0_s ;
	d1 <= ((not q3_s)and (not q1_s) and q0_s) or (q1_s and (not q0_s));
	d2 <= (q2_s and (not q1_s)) or ((not q2_s) and q1_s and q0_s)or (q2_s and (not q0_s));  
	d3 <= (q2_s and q1_s and q0_s) or (q3_s and (not q0_s));
	eo <= q3_s and (not q2_s) and not (q1_s) and (q0_s) and ei;
	q0<=q0_s;
	q1<=q1_s;
	q2<=q2_s;
	q3<=q3_s;
end ;
